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mic_huhu
Guest
嗨,所有A quesiton对你来说,如何处理这种情况。设计包含一些寄存器,但我不希望被删除,当我做synthsis。怎么办?如果我用“set_dont_touch”,我会得到一个网表的constains“SEQGEN”细胞。请问网表用于布局布线?由于许多感谢。 Jihnny
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